The SPI module can operate in all sleep modes by setting the run_in_standby option in the spi_config struct. In master mode, the SS pin(s) must be configured using the spi_slave_inst struct. If the receiver is disabled, the data input (MISO for master, MOSI for slave) can be used for other purposes. The SERCOM pads are automatically configured as seen in the table below. Leading edge is the first clock edge in a clock cycle and trailing edge is the last clock edge in a clock cycle. The table below shows the clock polarity (CPOL) and clock phase (CPHA) in the different modes.
There are four combinations of SCK phase and polarity with respect to serial data. Note In master mode, an address packet is written by the spi_select_slave function if the address_enabled configuration is set in the spi_slave_inst_config struct. If the device is asleep, it can be woken up by an address match in order to process the transaction. If the address does not match, the complete transaction is ignored. If there is a match, the MISO output is enabled and the transaction is processed. When the SPI slave is configured with address recognition, the first character in a transaction is checked for an address match. When SS line is driven high, the slave will not receive any additional data. If the receiver is enabled, the received character can be read from the receive buffer. If constant transmission of data is needed in SPI slave mode, the system clock should be faster than SCK. If the shift register has not been loaded with data, the current contents will be transmitted. As the SPI slave shift register is clocked by SCK, a minimum of three SCK cycles are needed from the time new data is written, until the character is ready to be shifted out. The data register can be updated at any time. When configured as a slave, the SPI interface will remain inactive with MISO tri-stated as long as the SS pin is driven high. If the receiver is enabled, the data is moved to the receive buffer at the completion of the frame and can be read.
As each character is shifted out from the master, a character is shifted in from the slave. Once this is done, a new character can be written. Writing a character will start the SPI clock generator, and the character is transferred to the shift register when the shift register is empty. When configured as a master, the SS pin will be configured as an output. The SPI character size is configurable to eight or nine bits. For a complete transaction, the master must shift N+1 characters. The N th slave connects its MISO back to the master. The MISO from the N-1 slaves is connected to the MOSI on the next slave. In this configuration, a common SS is provided to N slaves, enabling them simultaneously. It is also possible to connect all slaves in series. If the bus consists of several SPI slaves, they can be connected in parallel and the SPI master can use general I/O pins to control separate SS lines to each slave on the bus. To initiate a transaction, the master must pull this line low. The line where the data is shifted out from the master and into the slave. The line where the data is shifted out from the slave and into the master. In the figure below, the connection between one master and one slave is shown.
Note The specific features are only available in the driver when the selected device supports those features. After each data transfer, the master can synchronize to the slave by pulling the SS line high.ĭriver Feature Macro Definition Driver feature macro Data is always shifted from master to slave on the Master Out - Slave In (MOSI) line, and from slave to master on the Master In - Slave Out (MISO) line. Master and slave prepare data to be sent in their respective shift registers, and the master generates the required clock pulses on the SCK line to interchange data. The SPI master initiates a communication cycle by pulling low the Slave Select (SS) pin of the desired slave. The master initiates and controls all data transactions. It allows fast communication between a master device and one or more peripheral devices.Ī device connected to the bus must act as a master or a slave. The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. The outline of this documentation is as follows: The following devices can use this module: SERCOM (Serial Communication Interface).The following peripheral is used by this module: The following driver API modes are covered by this manual: This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration and management of the SERCOM module in its SPI mode to transfer SPI data frames.